Semiconductor package designs are typically constrained by the functionality of the device itself. The functions of a device determine the number of contacts with the outside environment and the number of contacts determines the number of “pins” required in the final package. However, semiconductor devices in “legacy” applications, meaning applications that have a lifespan extending beyond immediate replacement, sometimes need to evolve with technologies outside the existing application. In other cases, existing technologies cannot be used because of the constraints of legacy packaging.
An example of this is testing technology. Many legacy designs do not include any pins that are dedicated to testing. However, dedicated test pins are common in more recent semiconductor device designs. One testing technology developed by the Joint Test Action Group (JTAG) in the mid-1980s is the boundary-scan standard, described in IEEE 1149.1 since 1990. Boundary scan testing provides robust testing through embedded test circuitry at the chip level to form a complete board-level test protocol. With boundary-scan, complex assemblies can be accessed for in-system device programming and for diagnosing hardware problems. However, JTAG boundary-scan testing requires dedicated on-chip features and a set of dedicated connection pins. Such pins cannot be implemented in a legacy application where packaging constraints determine the number of connection pins available and determine the function of the available connection pins. Designs of devices destined for such legacy applications sometimes forgo in-system testability because of these constraints.
Testability is only one area in which a limited number of connections pins constraints the design of semiconductors. Another example is an increase in memory density within a RAM chip in an existing semiconductor package. Additional memory registers are often unreachable because of the limited number of address pins in the semiconductor package.
Not only do legacy packaging constraints prevent the addition of dedicated pins that can be used to add new functionality, but also, legacy packaging constraints require that pins maintain the dedicated functions specified in the legacy specification. For example each input pin that receives a certain input must still receive the same input, and use the same signal voltage levels as specified in the legacy specification. Accordingly, the dedicated pin functionality of each pin, and the signaling voltage must maintained in the new design.
Accordingly, there is a need for a method and apparatus that will allow for new functions to be implemented in semiconductor devices. Moreover, there is a need for a method an apparatus that meets the above needs and that does not require the use of additional dedicated pins and that maintains the dedicated functions of each pin. Also, there is a need for a method and apparatus that meets the above needs and that allows for testing of a semiconductor device using pins that have a dedicated function that is not a testing-related function. The present invention meets the above needs.